library ieee;

use ieee.std_logic_1164.all;
use work.cpu_utils.all;

entity dc is
	generic (
		input_lines: integer := 2;
		--line_size : integer := 1;
		Tpd: Time := unit_delay
	);--MUX2:4
	port(
		input: in bit_vector(input_lines-1 downto 0);
		output: out bit_vector(2**input_lines-1 downto 0)		--sel: in bit_vector(ord-1 downto 0)
	);
end entity;

architecture dc_arh of dc is
begin
	output<=(to_integer(input)=>'1',others=>'0') after Tpd;
end dc_arh;